The present invention relates generally to graphics processors, and more particularly to dynamic memory clock adjustments made by a graphics processor.
Graphics processors access and process huge volumes of data while generating video images for display on a monitor. Much of this data is stored and retrieved from a memory, such as a dynamic random-access memory (DRAM). Often these DRAMs are manufactured using a highly specialized process, and are therefore manufactured on an integrated circuit separate from the graphics processor itself. A graphics processor may store and retrieve data from one or more of these DRAMs. In order to facilitate the timing of data transfers between the graphics processor and memory, the graphics processor provides a clock signal, referred to as a memory clock (MCLK) to the memory circuits.
There are several conditions under which it is desirable for a graphics processor to change the frequency of a memory clock signal. For example, during startup and when power can be saved (or can no longer be saved), it is desirable to increase or decrease the frequency of the memory clock signal.
During startup, a splash screen is typically displayed identifying the operating system or other aspect of the computer system. This image is often at lower resolution, for example it may be compatible with the VGA standard. Once driver software is loaded into the computer system, images are displayed at a higher resolution. This change in resolution is facilitated in part by a change in the frequency of the memory clock signal. Also, if the screen image is not changing, for example when the text of a patent is being read by the user, the graphics processor may be able to run at a lower clock speed. This reduction in speed results in power savings that reduces battery drain in mobile applications and increases the mean time-before-failure of the graphics processor circuit.
When these changes in memory clock signal frequency occur, it is very desirable to not glitch or otherwise create a visual disturbance on the video monitor. Accordingly, what is needed are methods, circuits, and apparatus for changing a memory clock signal frequency without causing these disturbances. SUMMARY
Accordingly, embodiments of the present invention provide methods, circuits, and apparatus for changing a frequency of a memory clock signal provided to a graphics memory without causing a visual glitch or disturbance on a monitor. A specific embodiment provides multiple clock sources that may be multiplexed or selected to provide the memory clock signal to the graphics memory. The multiplexer switches from providing a first clock source as the memory clock signal to providing a second clock source as the memory clock signal. The first clock source changes its frequency of operation. After the first clock source settles or stabilizes, the multiplexer switches back to providing the first clock source as the memory clock signal.
An exemplary embodiment of the present invention provides a method of changing a frequency of a clock signal provided to a memory. This method includes generating a first clock signal having a first clock frequency by using a first clock source, and generating a second clock signal having a second clock frequency by using a second clock source. The first clock signal is selectively provided to the memory. After some time, the second clock signal is selectively provided to the memory. The frequency of the first clock signal is change to a third clock frequency. The first clock signal is then selectively provided to the memory.
Another exemplary embodiment of the present invention provides a method of changing a frequency of a clock signal by using a sequencer in a graphics processor. This method includes generating a first clock signal by using a first clock source, the first clock signal having a first frequency, and generating a first clock signal using a second clock source, the second clock signal having a second frequency. The method further provides selectively providing the first clock signal having the first frequency as a memory clock signal, determining the presence of a screen retrace or blanking period, requesting that a frame buffer interface cease activity, selectively providing the second clock signal having the second frequency as the memory clock signal, and changing the first frequency of the first clock signal to a third frequency. Again, the presence of a retrace is determined and a request is made to the frame buffer to cease activity. The first clock signal having the third frequency is then provided as the memory clock signal.
A further exemplary embodiment provides a method of changing a frequency of a clock signal provided to a memory. This method includes providing a first clock signal having a first frequency, the first clock signal selectively provided as a clock signal to the memory, the first clock signal generated by a first clock source, providing a second clock signal having a second frequency, the second clock signal generated by a second clock source, and providing a pixel clock signal having a third frequency. The method further provides determining whether a vertical retrace signal is active, changing the pixel clock signal such that the pixel clock has a fourth frequency, the fourth frequency being lower than the third frequency, selectively providing the second clock signal as the clock signal to the memory, and changing the pixel clock signal such that the pixel clock has the third frequency.
A better understanding of the nature and advantages of the present invention may be gained with reference to the following detailed description and the accompanying drawings. dr